Scholarly research

CERD seminar

CERD (Computer Education Research at Davis) is a weekly seminar started in January 2020 and co-founded by two former graduate students and myself. The topics are quite broad but they all relate to CS Education: presentation of academic papers or internal research projects or innovations in the classroom, external speakers, etc.

More information on our dedicated CERD website.

Pedagogical innovation

This line of education research is very broad, as we report on innovative teaching practices, curriculum development, etc.

  • Publication(s)
    • Design and Evaluation of “The Missing CS Class,” a Student-led Undergraduate Course to Reduce the Academia-industry Gap, Grant Gilson, Stephen Ott, Noah Rose Ledesma, Aakash Prabhu, Joël Porquet-Lupine, ACM SIGCSE 2022 (53rd ACM Technical Symposium on Computer Science Education) –34% acceptance rate, PDF
    • Group Work in (too) Large CS Classes with (too) Few Resources: an Experience Report, Joël Porquet-Lupine and Madison Brigham, ACM SIGCSE 2023 (54th ACM Technical Symposium on Computer Science Education), PDF
  • Talk(s)
    • Evaluating Group Work in Large CS Classes, Joël Porquet-Lupine, iCSTW 2022 (Illinois CS Summer Teaching Workshop), Slides

Study on gender and class participation

In this study, we are analyzing multiple quarters worth of class participation in two core CS classes (Data structures and algorithms, and Operating systems and system programming). The goal of this research is to determine whether or not there is a gender gap, explain it, and find solutions to mitigate it.

  • Publication(s)
    • Gender Differences in Class Participation in Core CS Courses, Madison Brigham and Joël Porquet-Lupine, ACM ITiCSE 2021 (26th Annual Conference on Innovation and Technology in Computer Science Education) –31% acceptance rate, PDF | Video
  • Talk(s)
    • Gender Differences in Class Participation in Core Computer Science Classes, Madison Brigham, UC Davis SoTL 2020 (5th Annual UC Davis Scholarship of Teaching and Learning Conference), Slides | Video

Software development for education

LupIO devices

Real I/O devices, even ancient ones (e.g., IDE controller, typical 16550 UART), are too complicated for educational purposes. They provide many configuration registers that are irrelevant when students use simple system emulators.

LupIO is a collection of educational I/O devices, which provides a suite of easy-to-understand but typical I/O devices (e.g., terminal, interrupt controller, timer, block device) that students can use –and study– in some of their undergraduate courses (e.g., courses on computer organization and assembly language, computer architecture, operating systems).

LupIO devices have now been implemented as virtual models in a few system emulators (e.g., QEMU, Gem5), and device drivers have also been implemented for a couple of different operating systems (e.g., Linux, XV6).

We are currently working on creating hardware models of LupIO devices.

  • Full specifications, implementation models, device drivers, etc.
  • Publication(s)
    • LupIO: a collection of education-friendly I/O devices, Joël Porquet-Lupine, WCAE 2021 (IEEE/ACM Workshop on Computer Architecture Education –held in conjuction with ISCA’2021), PDF | Video
    • Support for LupIO devices in gem5, Joël Porquet-Lupine, blog post on website


LupV is an education-friendly RISC-V based system emulator. The emulated system embeds a standard RV{32,64}GC-compatible processor (32-bit/64-bit RISC-V integer instruction set with support for multiply and divide, atomic operations, single- and double-precision floating point, and compressed instructions) and LupIO peripheral devices.

The goal of this project is to provide an easy to understand system emulator that students can use –and study– in some of their undergraduate courses (e.g., courses on computer organization and assembly language, computer architecture, operating systems). The emulator is yet powerful enough to boot Linux!

LupV’s source code and releases are available on


Interactive textbooks can have a real value when teaching programming languages. The problem is that existing interactive textbooks all require a server to interactively execute code at runtime, which is expensive for either the readers or the writers.

The goal of this project is to develop a new framework that runs entirely on the client’s side and can be used offline, therefore offering truly free interactive textbooks.


VRV started as a port of SPIM (a MIPS32 simulator which was very popular in the late 1990s-early 2000s, and was featured for a long time in the great “Computer Organization and Design” book by Hennessy and Patterson) to RISC-V.

While there are already plenty of educational RISC-V simulators out there (e.g., RARS, BRISC-V, WebRISC-V), none of them offer both command line and graphical interfaces. We found that it was incredibly helpful to have both, so that students can use the graphical interface, which the command line interface can be leveraged by an autograding script.

VRV was successfully used in ECS 50, our computer organization and assembly language course, during FQ23. We are now working on further improving the simulation engine, and developing a web interface.


This project’s goal is to help instructors map the floor plan of a lecture hall, and randomly assign seats to students for exams, while minimizing the chunk size (i.e., the number of students in a block of adjacent seats).

The tool is also able to handle relevant constraints, such as different types of seats (e.g., tablet on the left or the right, broken seats, ADA seats) and students with specific characteristics (e.g., left-handed students, ADA students).

While the first version of LupSeat was written in Python, we are currently working on a complete reimplementation as a web application in order to increase its usability and accessibility.

  • Source code and install instructions (Python version)
  • Publication(s)
    • LupSeat: A Randomized Seating Chart Generator to Prevent Exam Cheating [Poster], Joël Porquet-Lupine, Hiroya Gojo, Philip Breault, ACM SIGCSE 2022 (53rd ACM Technical Symposium on Computer Science Education), PDF | Poster


This tool is an online encoder/decoder for RISC-V instructions. Users can input RISC-V instructions in their assembly or binary format and get the full conversion from one to the other.

By early 2023, we should support the majority of the most common instruction sets and extensions: RV32I, RV64I, Zifencei, Zicsr, M, A, F, D.

Creative activities

Podcast #include<cs>

In 2019-2020 and with a small team of dedicated students, we created a podcast called #include<cs>. In each episode, we tell a story about Computer Science and Technology with an extra dose of fun and using non-technical language.

We took a long hiatus during the pandemic but as of December 2022, a new team is currently working on new episodes to be released in 2023.